#ifndef _VERILOG_UTILITY_H
#define _VERILOG_UTILITY_H

#include <cstdlib>
#include <limits>
#include <cassert>
#include <iostream>
#include <exception>
#include <vector>
#include <map>
#include <string>
#include <utility>


// Boost Library Headers

#include <boost/config.hpp>
#include <boost/graph/adjacency_list.hpp>
#include <boost/graph/graph_utility.hpp>
#include <boost/tuple/tuple.hpp>
#include <boost/utility.hpp>


#include "parser_helper.h"
#include "graphModel.h"
#include "circuitgraph.h"


class ExtendedVerilogParser: public VerilogParser
{

	public:
	
		ExtendedVerilogParser(string filename):VerilogParser(filename) {} ;
		
		int readVerilogFile (CircuitGraph&, std::map <std::string, LibParserCellInfo>&) ;
		
		netConnectivity getConnectivity (int) const ;
		
		void printNetConnectivity (CircuitGraph&) ;
		vector<netConnectivity> verilogConnectivity ;
                std::map <std::string, vertex_descriptor> instanceNodeMap;
                
	private:
		
		inline bool extractIsInput (std::string, std::vector<LibParserPinInfo>&) ;	
		inline void fillListSameFootPrint (std::string, std::vector<std::string>&, std::map <std::string, LibParserCellInfo>&) ;
		inline void extractFootPrint (std::string, std::string&, std::map <std::string, LibParserCellInfo>&) ;
		inline bool extractIsSequential (std::string, std::map <std::string, LibParserCellInfo>&) ;
		
		void readPrimaryInputs (CircuitGraph&) ;
		void readPrimaryOutputs (CircuitGraph&) ;
		void readWires (CircuitGraph&) ;
		void readCells (CircuitGraph&, std::map <std::string, LibParserCellInfo>& ) ;
                int gate_cnt;
};

#include "extendedverilogparser.hpp"

#endif
